DARPA Wants to Develop Secure IoT Chips

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The rise of the Internet of Things (IoT) has driven the creation of a rapidly growing number of accessible devices and a multitude of complex chip designs needed to enable them. With this rapid growth comes increased opportunity for cyber attackers to shift their attention from the software level to chips that enable complex capabilities across commercial and defense applications.

Despite growing recognition of the issue, there are no common tools, methods, or solutions for chip-level security currently in wide use. Incorporating security into chips is a manual, expensive, and cumbersome task that requires significant time and a level of expertise that is not readily available in most chip and system companies. The inclusion of security also often requires certain trade-offs with the typical design objectives, such as size, performance, and power dissipation. Further, modern chip design methods are unforgiving – once a chip is designed, adding security after the fact or making changes to address newly discovered threats is nearly impossible.

To ease the burden of developing secure chips, DARPA developed the Automatic Implementation of Secure Silicon (AISS) program. AISS aims to automate the process of incorporating scalable defense mechanisms into chip designs, while allowing designers to explore economics versus security trade-offs and maximize design productivity.

The objective of the program is to develop a design tool and IP ecosystem – which includes tool vendors, chip developers, IP licensers, and the open source community – that will allow security to be inexpensively incorporated into chip designs with minimal effort and expertise, ultimately making scalable on-chip security pervasive.

AISS seeks to create a novel, automated chip design flow that will allow the security mechanisms to scale consistently with the goals of the design.

The target system – or system on chip (SoC) – will be automatically generated, integrated, and optimized to meet the objectives of the application and security intent.

AISS seeks to address four specific attack surfaces that are most relevant. These include side channel attacks, reverse engineering attacks, supply chain attacks, and malicious hardware attacks.

AISS also seeks to ensure that the IP blocks that make up the chip remain secure throughout the design process and are not compromised as they move through the ecosystem, according to ecnmag.com.